| 1. |
- Becker, Matthias, 1986-, et al.
(author)
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A Generic Framework Facilitating Early Analysis of Data Propagation Delays in Multi-Rate Systems
- 2017
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In: The 23th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications RTCSA'17.
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Conference paper (peer-reviewed)abstract
- A majority of multi-rate real-time systems are constrained by a multitude of timing requirements, in addition to the traditional deadlines on well-studied response times. This means, the timing predictability of these systems not only depends on the schedulability of certain task sets but also on the timely propagation of data through the chains of tasks from sensors to actuators. In the automotive industry, four different timing constraints corresponding to various data propagation delays are commonly specified on the systems. This paper identifies and addresses the source of pessimism as well as optimism in the calculations for one such delay, namely the reaction delay, in the state-of-the-art analysis that is already implemented in several industrial tools. Furthermore, a generic framework is proposed to compute all the four end-to-end data propagation delays, complying with the established delay semantics, in a scheduler and hardware-agnostic manner. This allows analysis of the system models already at early development phases, where limited system information is present. The paper further introduces mechanisms to generate job-level dependencies, a partial ordering of jobs, which need to be satisfied by any execution platform in order to meet the data propagation timing requirements. The job-level dependencies are first added to all task chains of the system and then reduced to its minimum required set such that the job order is not affected. Moreover, a necessary schedulability test is provided, allowing for varying the number of CPUs. The experimental evaluations demonstrate the tightness in the reaction delay with the proposed framework as compared to the existing state-of-the-art and practice solutions.
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| 2. |
- Becker, Matthias, 1986-, et al.
(author)
-
A Many-Core based Execution Framework for IEC 61131-3
- 2015
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In: IECON 2015 - 41st Annual Conference of the IEEE Industrial Electronics Society. ; , s. 4525-4530
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Conference paper (peer-reviewed)abstract
- Programmable logic controllers are widely used for the control of automationsystems. The standard IEC 61131-3 defines the execution model as well as theprogramming languages for such systems. Nowadays, actuators and sensorsconnect to the programmable logic controller via automation buses. While suchbuses, as well as the sensors and actuators, become more and more powerful, ashift away from the current distributed operation of automation systems, closeto the field level, becomes possible. Instead, execution of complex controlfunctions can be relocated to more powerful hardware, and technologies. Thispaper presents an execution framework for IEC 61131-3, based on a many-coreprocessors. The presented execution model exploits the characteristics of theIEC 61131-3 applications as well as the characteristics of the many-core processor,yielding a predictable execution. We present the platform architectureand an algorithm to allocate a number of IEC 61131-3 conform applications.Experimental as well as simulation based evaluation is provided.
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| 3. |
- Becker, Matthias, 1986-, et al.
(author)
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Extending Automotive Legacy Systems with Existing End-to-End Timing Constraints
- 2018
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In: 14th International Conference on Information Technology : New Generations ITNG'17. - Cham : Springer International Publishing. - 9783319549774 ; , s. 597-605
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Conference paper (peer-reviewed)abstract
- Developing automotive software is becoming in- creasingly challenging due to continuous increase in its size and complexity. The development challenge is amplified when the industrial requirements dictate extensions to the legacy (previously developed) automotive software while requiring to meet the existing timing requirements. To cope with these challenges, sufficient techniques and tooling to support the modeling and timing analysis of such systems at earlier development phases is needed. Within this context, we focus on the extension of software component chains in the software architectures of automotive legacy systems. Selecting the sampling frequency, i.e. period, for newly added software components is crucial to meet the timing requirements of the chains. The challenges in selecting periods are identified. It is further shown how to automatically assign periods to software components, such that the end-to-end timing requirements are met while the runtime overhead is minimized. An industrial case study is presented that demonstrates the applicability of the proposed solution to industrial problems.
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| 4. |
- Becker, Matthias, 1986-, et al.
(author)
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Partitioning and Analysis of the Network-on-Chip on a COTS Many-Core Platform
- 2017
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In: 23rd IEEE Real-Time and Embedded Technology and Applications Symposium RTAS'17. - 9781509052691 ; , s. 101-112
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Conference paper (peer-reviewed)abstract
- Many-core processors can provide the computational power required by future complex embedded systems. However, their adoption is not trivial, since several sources of interference on COTS many-core platforms have adverse effects on the resulting performance. One main source of performance degradation is the contention on the Network-on-Chip, which is used for communication among the compute cores via the off- chip memory. Available analysis techniques for the traversal time of messages on the NoC do not consider many of the architectural features found on COTS platforms. In this work, we target a state-of-the-art many-core processor, the Kalray MPPA R . A novel partitioning strategy for reducing the contention on the NoC is proposed. Further, we present an analysis technique dedicated to the proposed partitioning strategy, which considers all architectural features of the COTS NoC. Additionally, it is shown how to configure the parameters for flow-regulation on the NoC, such that the Worst-Case Traversal Time (WCTT) is minimal and buffers never overflow. The benefits of our approach are evaluated based on extensive experiments that show that contention is significantly reduced compared to the unconstrained case, while the proposed analysis outperforms a state-of-the-art analysis for the same platform. An industrial case study shows the tightness of the proposed analysis.
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| 5. |
- Becker, Matthias, 1986-, et al.
(author)
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Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints
- 2018
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In: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC). - 9781509006021 ; , s. 560-567
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Conference paper (peer-reviewed)abstract
- Access to shared memory is one of the main chal- lenges for many-core processors. One group of scheduling strategies for such platforms focuses on the division of tasks’ access to shared memory and code execution. This allows to orchestrate the access to shared local and off-chip memory in a way such that access contention between different compute cores is avoided by design. In this work, an execution framework is introduced that leverages local memory by statically allocating a subset of tasks to cores. This reduces the access times to shared memory, as off-chip memory access is avoided, and in turn improves the schedulability of such systems. A Constrained Programming (CP) formulation is presented to selects the statically allocated tasks and generates the complete system schedule. Evaluations show that the pro- posed approach yields an up to 21% higher schedulability ratio than related work, and a case study demonstrates its applicability to industrial problems.
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| 6. |
- Becker, Matthias, 1986-, et al.
(author)
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Timing Analysis and Synthesis of Mixed Multi-Rate Effect Chains in MECHAniSer
- 2016
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In: Open Demo Session of Real-Time Systems located at Real Time Systems Symposium (RTSS) RTSS@Work 2016.
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Conference paper (peer-reviewed)abstract
- The majority of embedded control systems are modeled with several chains of independently triggered tasks, also known as multi-rate effect chains. These chains have often stringent end-to-end timing requirements that should be satisfied before running the system. MECHAniSer is one of the tools that supports end-to-end timing analysis of such chains. In addition, the tool provides the possibility to synthesize job-level dependencies for these chains such that all end-to-end timing requirements are satisfied. In this paper we showcase an extension of MECHAniSer that supports the analysis of mixed chains that contain a mix of independent and dependent tasks.
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